1. FIELD OF THE INVENTION
The present invention relates generally to metal-oxide semiconductor (MOS) dynamic random access memory (DRAM) circuits fabricated in the form of semiconductor integrated circuit chips, and more particularly to an improved DRAM cell having a charge amplifier for amplifying the charge output from a storage device within the memory cell.
2. DESCRIPTION OF THE PRIOR ART
The rapid advancement of semiconductor manufacturing technology in recent years can be clearly seen in the evolution of metal oxide silicon (MOS) dynamic random access memories (DRAMs) during this period. Early 1-kilobit (1024 bits) DRAMs using three or four transistors per memory cell were followed by 4-kilobit DRAMs employing the now widely utilized one-transistor-one-capacitor cell design.
Further improvements in bit density were achieved by enhanced processing techniques. Techniques such as the use of double level polysilicon conductors led to the production of the 16 kilobit DRAM.
Further recent advances in semiconductor manufacturing have allowed capacitative memory circuits to evolve from the 16 kilobit DRAM to commercially available semiconductor integrated circuit chips capable of storing 65,536 bits (64 kilobits). Quite recently, moreover, a few manufacturers have introduced a 256K (262,144 bits) memory unit on one chip, and the future prospect believed possible is the 1,000,000-bit chip.
Notwithstanding these recent advances in semiconductor memory technology, the desire to incorporate more and more functional circuitry on each individual chip, together with the commercial realities of yield, cost, and the like, have caused the semiconductor area available for circuitry to become extremely valuable. Concomitant with advances in memory cell fabrication is the development of improved techniques of packing more and more circuitry on smaller and smaller areas of silicon. Thus, when limits in fabrication techniques are encountered, industry focus turns to more efficient circuit design to reduce the component count and, in turn, to reduce the chip area upon which the circuit is formed.
One problem associated with high density DRAM circuits is the decrease in the signal strength produced by an individual memory cell which results when capacitor area is decreased as a means of shrinking cell size. As the cell signal is decreased, the sensitivity of the sense amplifier used to sense that signal during a read operation must be increased. The degree to which the sensitivity of a sense amplifier can be increased, however, is limited by the sense amplifier's susceptibility to faulty operation caused by electrical noise or alpha particle incursion.
One technique which can be used to compensate for a decreased cell signal is to amplify the cell output before it is received on the bit line to the sense amplifier. One such circuit is described in U.S. Pat. No. 4,168,536 and shown in FIG. 1. A memory cell circuit 10 utilizes a MOS transistor 12 to amplify a voltage developed across a resistor 14 when a "0" bit of information stored on a storage capacitor 16 is to be read. The disadvantage of this design is the added space required for the addition of the transistor 12 and the resistor 14. The reduction in capacitor size and chip area for the cell obtained by employing signal amplification is negated by the extra space required for the additional components.
Another attempt to scale down memory cell size includes the substitution of a bipolar transistor for the traditional storage capacitor. See, e.g., Chung-Yu Wu, "A New Dynamic Random Access Memory Cell Using a Bipolar MOS Composite Structure," IEEE Transactions on Electron Devices, Vol. ED-30, No. 8, August 1983, pp. 886-894. This composite structure, shown in FIG. 2 and described in more detail below, results, however, in a decrease in cell signal size.